High resistance cmos resistor

ABSTRACT

A high resistance CMOS resistor with a relatively small die size is provided. The CMOS resistor includes a p-field region disposed in a n-well of a substrate and a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well. The pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor. The CMOS resistor according to the present invention has a resistance of, for example, 10 kΩ-20 kΩ per square.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of a prior applicationSer. No. 10/823,238, filed Apr. 12, 2004. All disclosure of the U.S.application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor structure, and morespecifically to a high resistance CMOS resistor.

2. Description of Related Art

Many common circuits manufactured using CMOS process require resistorelements. In the area of analog circuits, resistor elements havinghigh-resistance values (100 kΩ-500 kΩ) are sometimes desired. The demandfor such resistors is especially common in the field of power-relativeanalog circuits.

In one common application, many power-relative analog circuits includevoltage dividers constructed from a pair of CMOS resistors. Such voltagedividers provide reference voltages that are stepped down from a supplyvoltage. The higher the resistance of the resistors is, the less standbypower will be consumed.

Currently, most widely used CMOS resistors are either junction resistorsor film resistors. Common junction resistor types include NW resistors,PW resistors, NDIFF(N+S/D) resistors, and PDIFF(N+S/D) resistors. Commonfilm resistor types include Poly resistors, M1 resistors, and M2resistors.

Though these resistors have satisfactory resistor characteristics, theirresistance is generally limited to 1 kΩ-5 kΩ per square. When ahigh-resistance element is required, it can be created either by usingextra die space, or by performing additional masking steps during themanufacturing process. However, neither of these alternatives isdesirable because they both increase the cost of manufacturing thecircuit.

Creating a high-resistance resistor (for example, from 100 kΩ to 500 kΩ)with traditional CMOS resistors is often commercially impractical due todie-size and cost restrictions. Therefore, there exists a need for aCMOS resistor having a significantly higher resistance per square thanexisting CMOS resistors. Furthermore, the process for manufacturing sucha CMOS resistor should not require any additional masking steps.

SUMMARY OF THE INVENTION

The present invention provides a CMOS resistor with a relatively smalldie-size. Such a CMOS component can reduce the cost and the die-size ofexisting circuits to fabricate many novel CMOS circuit designs.

While current CMOS resistors generally do not exceed 1 kΩ-5 kΩ persquare, the present invention presents a high resistance CMOS resistorhaving a high resistance, for example, from 10 k to 20 kΩ per square.Furthermore, unlike many existing processes of fabricating CMOSresistors, the process according to the present invention does notrequire any additional masking steps.

According to an embodiment of the present invention, a CMOS resistor isprovided. The CMOS resistor includes a p-field region disposed in an-well of a substrate and a pair of p-type contact regions respectivelydisposed beside a field oxide layer in the n-well. The pair of p-typecontact regions are respectively connected to two sides of the p-fieldregion as a first ohmic contact and a second ohmic contact for the CMOSresistor.

According to an embodiment of the present invention, a semiconductorstructure of a CMOS resistor is provided. The semiconductor structure ofthe CMOS resistor includes a p-type silicon substrate; an n-welldisposed in the p-type silicon substrate; a p-well disposed in anon-active area of the p-type silicon substrate; a first p-field regiondisposed in the p-well; a second p-field region disposed in the n-well;a field oxide layer disposed on the first p-field region and the secondp-field region; an n-type contact region disposed in the n-well; and atwo p-type contact regions respectively disposed beside the field oxidelayer in the n-well as a first ohmic contact and a second ohmic contact.

The CMOS resistor according to the present invention substantiallyreduces the standby power consumption of voltage dividers that arewidely used for generating reference voltages. A CMOS resistor having aresistance of 10 kΩ-20 kΩ per square could also substantially reduce themanufacturing and operating costs of many other existing circuits. Ahigher resistance per square could also make many new analog circuitdesigns involving high-resistance resistors possible.

However, the scope of this invention is no way limited to the field oflow standby-power electronics, or to voltage dividers. There are manyother types of circuits that could potentially benefit from the use ofsuch high-resistance CMOS resistors. Still further objects andadvantages will become apparent from a consideration of the ensuingdescription and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a cross-sectional view illustrating a step of forming ann-well in a p-type silicon substrate according to an embodiment of thepresent invention.

FIG. 2 is a cross-sectional view illustrating a step of forming a p-welland the n-well in the p-type silicon substrate according to anembodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a step of forming anactive area in the p-type silicon substrate according to an embodimentof the present invention.

FIG. 4 is a cross-sectional view illustrating a step of forming ap-field area in the n-well and forming another p-field area in thep-well according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a step of performing afield oxidation process according to an embodiment of the presentinvention.

FIG. 6 is a cross-sectional view illustrating a step of forming ann-type contact region according to an embodiment of the presentinvention.

FIG. 7 is a cross-sectional view illustrating a step of forming twop-type contact regions according to an embodiment of the presentinvention.

FIG. 8 is a cross-sectional view illustrating steps of forming two metalcontact plugs, and a passivation layer according to an embodiment of thepresent invention.

DESCRIPTION OF THE EMBODIMENTS

According to an embodiment of the present invention, a high resistanceCMOS resistor is provided. The process of fabricating the highresistance CMOS resistor comprises for example, the following steps. Ann-well and a p-well are formed in a p-type silicon substrate. A nitridelayer is then deposited over the p-type silicon substrate. Next,photolithography and etching steps are used to pattern the nitride layerto form a patterned mask layer for defining a non-active area and activearea over the p-type silicon substrate. In general, some p-type ions areimplanted into the non-active area of the p-well. Some channel-stops arealso implanted for increasing the isolation capability.

To form a CMOS resistor in another embodiment, the CMOS process includesinjecting the same p-type ions into the n-well to form a p-field region.After that, a field oxide is formed on the CMOS resistor. Heavily dopedp-type contact regions are formed as the ohmic contacts of the CMOSresistor, after the photolithography, etching, and implanting steps.Finally, two contact openings and two metal contact plugs are formed toelectrically connect two ohmic contacts of the CMOS resistor. Thus, ahigh resistance resistor is formed without requiring any additionalmasking steps. In addition, this process is fully compatible withstandard CMOS processes.

Referring now to the drawings wherein the contents are for purposes ofillustrating the preferred embodiment of the invention only and not forpurposes of limiting the same. Referring to FIG. 1, phosphorus ions areimplanted in a p-type silicon substrate 20 to form an n-well 22. Thep-type silicon substrate 20 is doped with boron ions to achieve aresistance of 8Ω-12Ω per cm. The n-well 22 can be formed via well-knownphotolithography, etching and implantation process as follows. Aphotoresist layer is formed over the p-type silicon substrate 20. Next,the photoresist layer is exposed using a mask to expose predeterminedportions of the photoresist layers. Next, the exposed photoresist isetched to remove the predetermined portions of the p-type siliconsubstrate 20. Next, an ion implementation is then carried out using anenergy level of 100 KeV using phosphorus ions with a dosage levelranging from 6×10¹² to 9×10¹² ions/cm².

Next, as FIG. 2 shows, boron ions are implanted into the p-type siliconsubstrate 20 to form a p-well 30. The implantation is done using anenergy level of 40 KeV, with a dosage level ranging from 8×10¹² to9×10¹² ions/cm². Next, a thermal annealing process is carried at, forexample, a temperature of about 1150° C., to diffuse the n-type andp-type ions into the respective regions within the p-type siliconsubstrate 20.

As shown in FIG. 3, a pad oxide layer 40 having a thickness of about 350angstroms is formed over the surface of the p-type silicon substrate 20.The pad oxide layer 40 is formed, for example but limited to, byperforming a thermal oxidation at a temperature of 900° C. Next, anitride layer having a thickness of 1250 angstroms is then deposited ata temperature of 850° C. over the pad oxide layer 40. Next, the nitridelayer is etched via photolithography and etching process to form apatterned mask layer 42 over the surface of the pad oxide layer 40. Thepatterned mask 42 serves as a mask in the subsequent process.

Hereinafter, as FIG. 4 shows, performing an ion implantation process 46using the patterned mask layer 42 as the mask forms a p-field region 50and a p-field region 52. Boron ions are then implanted at an energylevel of 50 KeV with a dosage level ranging from 4×10¹³ to 6×10¹³ions/cm².

As shown in FIG. 4, the p-field region 50 and the p-field region 52 areformed below the pad oxide layer 40. As it will be well known to thoseskilled in the art that the p-field implantation is a standard CMOSprocess. In general, the p-field region 50 is implanted into the p-well30. The p-field region 50 acts as device isolation layers (ie, channelstops). However, it should be understood that the p-field implantationcould also be done in an unconventional manner. The p-field region 52 isimplanted into the n-well 22 in order to form a window into the n-well22. The p-field region 52 forms a CMOS resistor. This step enables theCMOS resistor, according to the present invention, to be built withoutthe use of any additional masking steps. A field oxidation process isperformed at a temperature of 980° C. to form a field oxide layer 60over the p-type silicon substrate 20 as shown in FIG. 5. The field oxidelayer 60 is grown to a thickness of about 5000-6000 angstroms. When thisstep is completed, the patterned mask layer 42 will be removed.

Now turning to FIG. 6, an n-type contact region 70 is formed in then-well 22. For example, the n-type contact region 70 can be formed via aconventional photolithography and etching process to form a patternedmask layer exposing predetermined portion of the n-well 22. Arsenic ionsare implanted at an energy level of 80 KeV, with a dosage level in arange of 4×10¹⁵ to 6×10¹⁵ ions/cm². The implantation is done withheavier arsenic atoms because this forms the n-type contact region 70with a shallow depth. This forms a window for the field oxide layer 60.

As shown in FIG. 7, after forming the n-type contact region 70, p-typecontact regions 80 and 82 are formed in the n-well 22. Similarly, thep-type contact region 80 and p-type contact region 82 can also be formedby performing conventional photolithography and etching process to forma patterned mask layer, and then using the patterned mask layer as mask.Boron ions are implanted at an energy level of 25 KeV with a dosagelevel ranging from 2×10¹⁵ to 4×10¹⁵ ions/cm².

FIG. 7 shows a cross-sectional view of the p-type contact region 82implanted in the n-well 22. Therefore, the p-type contact region 80 andthe p-type contact region 82 are formed in the n-well 22. The p-typecontact regions 80 and 82 act as two ohmic contacts of the CMOSresistor. And this completes the fabrication of a high resistance CMOSresistor.

Next, contact openings and metal contact plugs are formed toelectrically contact the two ohmic contacts of the CMOS resistor. Asshown in FIG. 8, a boro-phospho-silicate glass (BPSG) layer 90 isdeposited to form two contact openings exposing a portion of the n-typecontact region and the two p-type contact regions. For example, thethickness of the BPSG layer 90 is in the range of 5,000 to 8,000angstroms. Subsequently, a metal layer 92 having a thickness of 5,000angstroms is sputtered over the BPSG layer 90. For example, the metallayer 92 is an AlSiCu layer. Furthermore, two metal contact plugsdisposed in the contact openings to electrically connect to the firstohmic contact and the second ohmic contact of the CMOS resistor.Finally, an oxide layer 94 having a thickness in the range of 5,000 to10,000 angstroms is deposited over the resulting structure. The oxidelayer 94 serves as a passivation layer to protect the CMOS resistor anddisposes over the contact plugs covering the CMOS resistor.

Thus, a CMOS resistor having high resistance is formed without anyadditional masking steps. In addition, this process is fully compatiblewith standard CMOS processes. This CMOS resistor will have a resistanceof about 10 kΩ-20 kΩ per square.

It is to be understood that this process of fabricating a CMOS resistoraccording to the present invention is described for the purpose ofillustrating rather than limiting the scope of the present invention.

Thus, it will be apparent to those skilled in the art, that the methodfor manufacturing a CMOS resistor according to the present inventioncould also be applied to manufacture an n-field resistor in an n-typesilicon substrate, without departing from the spirit or the scope of theinvention.

In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims or their equivalents.

1. A semiconductor structure of a CMOS resistor, comprising: a p-typesilicon substrate; an n-well disposed in the p-type silicon substrate; ap-well disposed in a non-active area of the p-type silicon substrate; afirst p-field region disposed in the p-well; a second p-field regiondisposed in the n-well; a field oxide layer disposed on the firstp-field region and the second p-field region; an n-type contact regiondisposed in the n-well; and a pair of two p-type contact regionsrespectively disposed beside the field oxide layer in the n-well as afirst ohmic contact and a second ohmic contact.
 2. The semiconductorstructure according to claim 1, further comprising a patterned BPSGlayer formed to build two contact openings exposing a portion of then-type contact region and the two p-type contact regions.
 3. Thesemiconductor structure according to claim 2, further comprising twometal contact plugs disposed in the contact openings to electricallyconnect to the first ohmic contact and the second ohmic contact of theCMOS resistor.
 4. The semiconductor structure according to claim 3,further comprising a passivation layer deposited over the contact plugscovering the CMOS resistor.
 5. The semiconductor structure according toclaim 1, wherein the CMOS resistor is formed compatibly with a standardCMOS process.
 6. A semiconductor structure of a CMOS resistor,comprising: an n-well; a first p-type contact region disposed in then-well; a second p-field region coupled to the first p-type contactregion; a second p-type contact region coupled to the second p-fieldregion; and a field oxide layer formed on the second p-field region. 7.The semiconductor structure according to claim 6, further comprising ann-type contact region coupled to the first p-type contact region.
 8. Thesemiconductor structure according to claim 6, further comprising ap-well coupled to the n-well.
 9. The semiconductor structure accordingto claim 8, further comprising a first p-field region formed on thep-well.
 10. The semiconductor structure according to claim 9, furthercomprising a field oxide layer formed on the second p-field region. 11.A CMOS resistor, comprising: a p-field region disposed in a n-well of asubstrate; and a pair of p-type contact regions respectively disposedbeside a field oxide layer in the n-well, wherein the pair of p-typecontact regions are respectively connected to two sides of the p-fieldregion as a first ohmic contact and a second ohmic contact for the CMOSresistor.